Sciweavers

1529 search results - page 151 / 306
» On Timing Analysis of Combinational Circuits
Sort
View
ICPPW
2009
IEEE
13 years 6 months ago
Improvement of Messages Delivery Time on Vehicular Delay-Tolerant Networks
Vehicular Delay-Tolerant Networks (VDTNs) are an application of the Delay-Tolerant Network (DTN) concept, where the movement of vehicles and their message relaying service is used ...
Vasco Nuno da Gama de Jesus Soares, Joel Jos&eacut...
CIVR
2006
Springer
172views Image Analysis» more  CIVR 2006»
13 years 12 months ago
Retrieving Shapes Efficiently by a Qualitative Shape Descriptor: The Scope Histogram
Abstract. Efficient image retrieval from large image databases is a challenging problem. In this paper we present a method offering constant time complexity for the comparison of t...
Arne Schuldt, Björn Gottfried, Otthein Herzog
DAC
2005
ACM
14 years 9 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
NOCS
2008
IEEE
14 years 2 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
STACS
2009
Springer
14 years 3 months ago
Semi-Online Preemptive Scheduling: One Algorithm for All Variants
We present a unified optimal semi-online algorithm for preemptive scheduling on uniformly related machines with the objective to minimize the makespan. This algorithm works for a...
Tomás Ebenlendr, Jiri Sgall