1529 search results - page 171 / 306 » On Timing Analysis of Combinational Circuits |
TVLSI
2008
13 years 8 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
IPL
2007
13 years 8 months ago
2007
We deal with the problem of maintaining a dynamic graph so that queries of the form “is there an edge between u and v?” are processed fast. We consider graphs of bounded arbor...
HCI
2007
13 years 9 months ago
2007
This paper describes a hybrid methodology to study users in ongoing relationships based on three levels of user data analysis. Most user-centered design methods are ideal for the a...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...