1444 search results - page 197 / 289 » On Variations of Power Iteration |
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
—A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorith...
DSD
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern day applications require use of multi-processor systems for reasons of scalability and power efficiency. As more and more applications are integrated on a single device, m...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
IOLTS
2006
IEEE
14 years 2 months ago
2006
IEEE
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
MTDT
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...