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» On Variations of Power Iteration
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PATMOS
2005
Springer
14 years 3 months ago
Efficient Simulation of Power/Ground Networks with Package and Vias
As the number of metal layers and the frequency of VLSI continue to increase, the voltage droop on both the package and vias is becoming more pronounced. This paper analyzes the nu...
Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Ta...
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 10 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
JSAC
2006
63views more  JSAC 2006»
13 years 10 months ago
Multicarrier multiple access is sum-rate optimal for block transmissions over circulant ISI channels
Abstract--Multicarrier multiple access with channel knowledge and prescribed power at the transmitters is shown to maximize the sum-rate for circulant intersymbol-interference (ISI...
Shuichi Ohno, Georgios B. Giannakis, Zhi-Quan Luo
DAC
2008
ACM
14 years 11 months ago
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
Ümit Y. Ogras, Diana Marculescu, Radu Marcule...
ASPDAC
2009
ACM
142views Hardware» more  ASPDAC 2009»
14 years 4 months ago
On the futility of statistical power optimization
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this...
Jason Cong, Puneet Gupta, John Lee