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» On a vector q-d algorithm
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100
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DATE
2006
IEEE
82views Hardware» more  DATE 2006»
15 years 8 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito
ICPR
2006
IEEE
15 years 8 months ago
Regularized Locality Preserving Learning of Pre-Image Problem in Kernel Principal Component Analysis
In this paper, we address the pre-image problem in kernel principal component analysis (KPCA). The preimage problem finds a pattern as the pre-image of a feature vector defined in...
Weishi Zheng, Jian-Huang Lai
IPPS
2006
IEEE
15 years 8 months ago
A calculus of functional BSP programs with projection
Bulk Synchronous Parallel ML (BSML) is an extension of the functional language Objective Caml to program Bulk Synchronous Parallel (BSP) algorithms. It is deterministic, deadlock ...
Frédéric Loulergue
117
Voted
ATS
2005
IEEE
100views Hardware» more  ATS 2005»
15 years 8 months ago
Finite State Machine Synthesis for At-Speed Oscillation Testability
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, ...
CEC
2005
IEEE
15 years 8 months ago
Genetic programming approach for fault modeling of electronic hardware
This paper presents two variants of Genetic Programming (GP) approaches for intelligent online performance monitoring of electronic circuits and systems. Reliability modeling of el...
Ajith Abraham, Crina Grosan