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» On achieving optimal throughput with network coding
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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 10 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
SAMOS
2005
Springer
14 years 2 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 5 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
ISM
2005
IEEE
88views Multimedia» more  ISM 2005»
14 years 2 months ago
Hybrid Bitrate/PSNR Control for H.264 Video Streaming to Roaming Users
In wireless communications, the available throughput depends on several parameters, like physical layer, base station distance, fading and interference. Users experience changes i...
Fabio De Vito, Federico Ridolfo, Juan Carlos De Ma...
TWC
2008
99views more  TWC 2008»
13 years 8 months ago
Robust transmit processing for frequency-selective fading channels with imperfect channel feedback
Reliable channel state information at the transmitter (CSIT) can improve the throughput of wireless networks significantly. In a realistic scenario, there is a mismatch between th...
Christof Jonietz, Wolfgang H. Gerstacker, Robert S...