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» On computational limitations of neural network architectures
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ICDE
2009
IEEE
114views Database» more  ICDE 2009»
14 years 10 months ago
On Efficient Query Processing of Stream Counts on the Cell Processor
In recent years, the sketch-based technique has been presented as an effective method for counting stream items on processors with limited storage and processing capabilities, such...
Dina Thomas, Rajesh Bordawekar, Charu C. Aggarwal,...
NOCS
2007
IEEE
14 years 3 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston
DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 2 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
IMC
2003
ACM
14 years 2 months ago
In search of path diversity in ISP networks
Internet Service Providers (ISPs) can exploit path diversity to balance load and improve robustness. Unfortunately, it is difficult to evaluate the potential impact of these appr...
Renata Teixeira, Keith Marzullo, Stefan Savage, Ge...
IROS
2007
IEEE
138views Robotics» more  IROS 2007»
14 years 3 months ago
On-demand sharing of a high-resolution panorama video from networked robotic cameras
— Due to their flexibility in coverage and resolution, networked robotic cameras become more and more popular in applications such as natural observation, security surveillance,...
Ni Qin, Dezhen Song