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ISLPED
1997
ACM
116views Hardware» more  ISLPED 1997»
14 years 1 months ago
Power reduction techniques for a spread spectrum based correlator
This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider...
David Garrett, Mircea R. Stan
ICCD
2008
IEEE
120views Hardware» more  ICCD 2008»
14 years 5 months ago
Improved combined binary/decimal fixed-point multipliers
Abstract— Decimal multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper pres...
Brian J. Hickmann, Michael J. Schulte, Mark A. Erl...
GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
14 years 2 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
TWC
2008
209views more  TWC 2008»
13 years 8 months ago
Application of Nonbinary LDPC Cycle Codes to MIMO Channels
In this paper, we investigate the application of nonbinary low-density parity-check (LDPC) cycle codes over Galois field GF(q) to multiple-input multiple-output (MIMO) channels. Tw...
Ronghui Peng, Rong-Rong Chen
GECCO
2006
Springer
164views Optimization» more  GECCO 2006»
14 years 19 days ago
Biobjective evolutionary and heuristic algorithms for intersection of geometric graphs
Wire routing in a VLSI chip often requires minimization of wire-length as well as the number of intersections among multiple nets. Such an optimization problem is computationally ...
Rajeev Kumar, Pramod Kumar Singh, Bhargab B. Bhatt...