The first polynomial time algorithm (O(n4 )) for modular decomposition appeared in 1972 [8] and since then there have been incremental improvements, eventually resulting in linear...
Michel Habib, Fabien de Montgolfier, Christophe Pa...
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
This work focuses on the basic stochastic decomposition (SD) algorithm of Higle and Sen [J.L. Higle, S. Sen, Stochastic Decomposition, Kluwer Academic Publishers, 1996] for two-st...
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reco...