This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
This paper analyses HPSS performance and, to a lesser extent, characterizes the SDSC HPSS workload, utilizing per-file transfer logs. The performance examined includes disk cache ...
Wayne Schroeder, Richard Marciano, Joe Lopez, Mich...
The popularity of the World-Wide-Web has increased dramatically in the past few years. Web proxy servers have an important role in reducing server loads, network traffic, and clie...
George Pallis, Athena Vakali, Lefteris Angelis, Mo...
— Video streaming on mobile devices such as PDA’s, laptop PCs, pocket PCs and cell phones is becoming increasingly popular. These mobile devices are typically constrained by th...
Piyush Parate, Lakshmish Ramaswamy, Suchendra M. B...
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...