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» On modeling top-down VLSI design
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FCCM
2009
IEEE
170views VLSI» more  FCCM 2009»
13 years 5 months ago
Generic Software Framework for Adaptive Applications on FPGAs
Adaptive systems are set to become more mainstream, as numerous practical applications in the communications domain emerge. FPGAs offer an ideal implementation platform, combining...
Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda...
VLSID
2010
IEEE
181views VLSI» more  VLSID 2010»
13 years 11 months ago
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients
We propose a method for diagnosis of parametric faults in analog circuits using polynomial coefficients of the circuit model [15]. As a sequel to our recent work [14], where circ...
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
GLVLSI
2007
IEEE
186views VLSI» more  GLVLSI 2007»
13 years 7 months ago
Block placement to ensure channel routability
Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total widt...
Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghav...
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
14 years 8 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
DFT
2005
IEEE
72views VLSI» more  DFT 2005»
14 years 1 months ago
Soft Error Modeling and Protection for Sequential Elements
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
Hossein Asadi, Mehdi Baradaran Tahoori