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» On modeling top-down VLSI design
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ISVLSI
2005
IEEE
101views VLSI» more  ISVLSI 2005»
14 years 1 months ago
eWatch: Context Sensitive System Design Case Study
In this paper, we introduce a novel context sensitive system design paradigm. Multiple sensors/ computational architecture, in the form of our eWatch device, is used to infer the ...
Asim Smailagic, Daniel P. Siewiorek, Uwe Maurer, A...
VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
14 years 8 months ago
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
Haris Lekatsas, Jörg Henkel
CODES
2008
IEEE
13 years 9 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
SBCCI
2003
ACM
113views VLSI» more  SBCCI 2003»
14 years 24 days ago
Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment
IP reuse is essential in embedded SoC design. IP components may be described in different modeling languages and present heterogeneous interfaces. The Tangram environment supports...
Uilian Rafael Feijo Souza, Josue Klafke Sperb, Bra...
IJCNN
2008
IEEE
14 years 1 months ago
Wafer-scale integration of analog neural networks
Abstract— This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time a...
Johannes Schemmel, Johannes Fieres, Karlheinz Meie...