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» On modeling top-down VLSI design
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VLSID
2005
IEEE
120views VLSI» more  VLSID 2005»
14 years 1 months ago
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattachar...
DATE
1999
IEEE
129views Hardware» more  DATE 1999»
13 years 12 months ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 11 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
RECONFIG
2008
IEEE
107views VLSI» more  RECONFIG 2008»
14 years 1 months ago
Fast Implementation of a Bio-inspired Model for Decentralized Gathering
In the context of the emergence of alternative computing resources to address the challenge of the upcoming end of Moore’s law, we consider the feasibility of gathering computat...
Bernard Girau, Cesar Torres-Huitzil
DFT
1999
IEEE
75views VLSI» more  DFT 1999»
13 years 12 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu