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» On performance limitations of congestion control
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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 4 days ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
IJMMS
2006
93views more  IJMMS 2006»
13 years 7 months ago
Presence, workload and performance effects of synthetic environment design factors
There remains a limited understanding of factors in presence and its relation to performance. This research examined a range of synthetic environment (SE) design features (viewpoi...
Ruiqi Ma, David B. Kaber
TMC
2008
101views more  TMC 2008»
13 years 7 months ago
The Mathematical Theory of Dynamic Load Balancing in Cellular Networks
While many interesting dynamic load balancing schemes have been proposed for efficient use of limited bandwidth and to increase the capacity of congested or hot spots (or cells) in...
Ozan K. Tonguz, Evsen Yanmaz
HCI
2009
13 years 5 months ago
Neurocognitive Workload Assessment Using the Virtual Reality Cognitive Performance Assessment Test
The traditional approach to assessing neurocognitive performance makes use of paper and pencil neuropsychological assessments. This received approach has been criticized as limited...
Thomas D. Parsons, Louise Cosand, Christopher G. C...
SIES
2008
IEEE
14 years 2 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl