46 search results - page 7 / 10 » On pipelining dynamic instruction scheduling logic |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
TVLSI
2002
13 years 7 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
ISCA
2003
IEEE
14 years 23 days ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
ICS
2001
Tsinghua U.
13 years 12 months ago
2001
Tsinghua U.
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...