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» On reducing load store latencies of cache accesses
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WMPI
2004
ACM
14 years 1 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 27 days ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
HPCA
1998
IEEE
13 years 12 months ago
The Effectiveness of SRAM Network Caches in Clustered DSMs
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...
Adrian Moga, Michel Dubois
ESCIENCE
2005
IEEE
14 years 1 months ago
Iteration Aware Prefetching for Remote Data Access
1 Although processing speed, storage capacity and network bandwidth are steadily increasing, network latency remains a bottleneck for scientists accessing large remote data sets. T...
Philip J. Rhodes, Sridhar Ramakrishnan
WISE
2002
Springer
14 years 16 days ago
An Update-Risk Based Approach to TTL Estimation in Web Caching
Web caching is an important technique for accelerating web applications and reducing the load on the web server and the network through local cache accesses. As in the traditional...
Jeong-Joon Lee, Kyu-Young Whang, Byung Suk Lee, Ji...