315 search results - page 9 / 63 » On reducing load store latencies of cache accesses |
CF
2004
ACM
13 years 11 months ago
2004
ACM
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
ICPP
1999
IEEE
13 years 12 months ago
1999
IEEE
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...