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» On reducing misspeculations in a pipelined scheduler
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VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
14 years 11 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
JEC
2006
61views more  JEC 2006»
13 years 10 months ago
Time-constrained loop scheduling with minimal resources
Many applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
HPDC
1998
IEEE
14 years 3 months ago
Metascheduling: A Scheduling Model for Metacomputing Systems
Abstract Metacomputing is the seamless application of geographically-separated distributed computing resources to user applications. We consider the scheduling of metaapplications;...
Jon B. Weissman
SPAA
1997
ACM
14 years 3 months ago
Pipelining with Futures
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
Guy E. Blelloch, Margaret Reid-Miller
EUROPAR
2010
Springer
13 years 11 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...