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VTS
2007
IEEE
203views Hardware» more  VTS 2007»
14 years 1 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba
SPIN
2005
Springer
14 years 26 days ago
Sound Transaction-Based Reduction Without Cycle Detection
Vladimir Levin, Robert Palmer, Shaz Qadeer, Sriram...
DAC
1999
ACM
13 years 11 months ago
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits
Valeria Bertacco, Maurizio Damiani, Stefano Quer