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On test coverage of path delay faults
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ISLPED
2007
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Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
14 years 12 days ago
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Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
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