Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift data capturing clock edge to tolerate NBTI-induced delay degradation on critical timing paths. VL-adder operates with a fixed supply voltage and clock period, avoiding the high design and manufacturing costs incurred by existing NBTI-tolerant techniques. Compared to other related lower-power adder designs, VL-adder technique always provides better energy efficiency through the whole chip lifetime with very limited performance degradation (4.6% or less). Categories and Subject Descriptors B.8.1 [Performance and Reliability]: Reliability, Testing, and Fault-Tolerance General Terms: Performance, Design, Reliability

• Type: Conference
• Year: 2007
• Where: ISLPED
• Authors: Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
• Keywords: Dominant Reliability Concern, Hardware, ISLPED 2007, Nanoscale Pmos Transistors, Negative Bias Temperature Instability