166 search results - page 12 / 34 » On testing delay faults in macro-based combinational circuit... |
ISQED
2003
IEEE
14 years 1 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ICCAD
1990
IEEE
13 years 12 months ago
1990
IEEE
Partial detectability profiles are formed by randomly sampling each fault's detectability and are used in estimating the fault coverage of random input test vectors on combin...
VTS
1996
IEEE
13 years 12 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
DATE
1999
IEEE
14 years 3 days ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...