166 search results - page 20 / 34 » On testing delay faults in macro-based combinational circuit... |
VTS
2000
IEEE
14 years 5 days ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...
VTS
2002
IEEE
14 years 21 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ET
2000
13 years 7 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
GLVLSI
2010
IEEE
14 years 27 days ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...