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ATS
2010
IEEE
229views Hardware» more  ATS 2010»
13 years 5 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...
DAC
2007
ACM
14 years 8 months ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that g...
Qunzeng Liu, Sachin S. Sapatnekar
DFT
1997
IEEE
93views VLSI» more  DFT 1997»
14 years 5 hour ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...
EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
13 years 11 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
CSREAESA
2006
13 years 9 months ago
Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy
- Triple Modular Redundancy is widely used in dependable systems design to ensure high reliability against soft errors. Conventional TMR is effective in protecting sequential circu...
Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wan...