418 search results - page 17 / 84 » On the Adders with Minimum Tests |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
SIGMETRICS
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
EH
2003
IEEE
14 years 29 days ago
2003
IEEE
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
ISLPED
1999
ACM
14 years 7 hour ago
1999
ACM
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
KR
1992
Springer
13 years 11 months ago
1992
Springer
While it has been realized for quite some time within AI that abduction is a general model of explanation for a variety of tasks, there have been no empirical investigations into ...