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» On the Architecture of System Verification Environments
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FMSD
1998
74views more  FMSD 1998»
13 years 7 months ago
A Formal Verification Environment for Railway Signaling System Design
Cinzia Bernardeschi, Alessandro Fantechi, Stefania...
DAC
1996
ACM
13 years 11 months ago
State Reduction Using Reversible Rules
We reduce the state explosion problem in automatic verification of finite-state systems by automatically collapsing subgraphs of the aph into abstract states. The key idea of the ...
C. Norris Ip, David L. Dill
CORR
2007
Springer
127views Education» more  CORR 2007»
13 years 7 months ago
Common Reusable Verification Environment for BCA and RTL Models
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
Giuseppe Falconeri, Walid Naifer, Nizar Romdhane
LISA
2007
13 years 9 months ago
ATLANTIDES: An Architecture for Alert Verification in Network Intrusion Detection Systems
We present an architecture1 designed for alert verification (i.e., to reduce false positives) in network intrusion-detection systems. Our technique is based on a systematic (and a...
Damiano Bolzoni, Bruno Crispo, Sandro Etalle