1795 search results - page 157 / 359 » On the Complexity of Circuit Satisfiability |
164
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ISQED
2005
IEEE
15 years 11 months ago
2005
IEEE
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
152
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SLIP
2003
ACM
15 years 11 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
200
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TABLEAUX
1998
Springer
15 years 10 months ago
1998
Springer
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
156
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DAC
1994
ACM
15 years 10 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
161
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DAC
2009
ACM
15 years 9 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...