In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...