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» On the Complexity of Circuit Satisfiability
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ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
14 years 1 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
DAC
1996
ACM
14 years 28 days ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant
TVLSI
2002
366views more  TVLSI 2002»
13 years 8 months ago
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
DAC
2007
ACM
14 years 9 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ISMVL
1997
IEEE
99views Hardware» more  ISMVL 1997»
14 years 29 days ago
Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
Riccardo Mariani, Roberto Roncella, Roberto Salett...