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» On the Complexity of Error Explanation
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ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
15 years 9 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
NIS
1998
131views more  NIS 1998»
15 years 4 months ago
Dynamic Memory Allocation for Large Query Execution
The execution time of a large query depends mainly on the memory utilization which should avoid disk accesses for intermediate results. Poor memory management can hurt performance ...
Luc Bouganim, Olga Kapitskaia, Patrick Valduriez
ECCV
2004
Springer
16 years 6 months ago
Towards Intelligent Mission Profiles of Micro Air Vehicles: Multiscale Viterbi Classification
In this paper, we present a vision system for object recognition in aerial images, which enables broader mission profiles for Micro Air Vehicles (MAVs). The most important factors ...
Sinisa Todorovic, Michael C. Nechyba
ICIP
2005
IEEE
16 years 6 months ago
A dynamic Bezier curve model
Bezier curves (BC) are fundamental to a wide range of applications from computer-aided design through to object shape descriptions and surface mapping. Since BC only consider glob...
Ferdous Ahmed Sohel, Laurence S. Dooley, Gour C. K...
HPCA
2009
IEEE
16 years 5 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco