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» On the Complexity of Loop Fusion
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EUROPAR
2006
Springer
14 years 19 days ago
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...
Alban Douillet, Hongbo Rong, Guang R. Gao
CODES
2004
IEEE
14 years 21 days ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
IEEECIT
2010
IEEE
13 years 7 months ago
Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems
—As the need for embedded systems to interact with other systems is growing fast, we see great opportunities in introducing the hardware-in-the-loop technique to the field of ha...
Dogan Fennibay, Arda Yurdakul, Alper Sen
ICS
2004
Tsinghua U.
14 years 2 months ago
Applications of storage mapping optimization to register promotion
Storage mapping optimization is a flexible approach to folding array dimensions in numerical codes. It is designed to reduce the memory footprint after a wide spectrum of loop tr...
Patrick Carribault, Albert Cohen
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 2 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...