Sciweavers

544 search results - page 49 / 109
» On the Complexity of Loop Fusion
Sort
View
ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
14 years 1 months ago
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynam...
Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
14 years 14 days ago
Vector instruction set support for conditional operations
Vector instruction sets are receiving renewed interest because of their applicability to multimedia. Current multimedia instruction sets use short vectors with SIMD implementation...
James E. Smith, Greg Faanes, Rabin A. Sugumar
JSAC
2008
124views more  JSAC 2008»
13 years 8 months ago
Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding
Abstract-- We explore the performance and hardware complexity tradeoffs associated with performing iterative multipleinput multiple-output (MIMO) detection using a sphere decoder a...
Hyungjin Kim, Dong-U Lee, John D. Villasenor
TROB
2008
146views more  TROB 2008»
13 years 8 months ago
Mapping a Suburb With a Single Camera Using a Biologically Inspired SLAM System
This paper describes a biologically inspired approach to vision-only simultaneous localization and mapping (SLAM) on ground-based platforms. The core SLAM system, dubbed RatSLAM, i...
Michael Milford, Gordon Wyeth
EMSOFT
2010
Springer
13 years 7 months ago
Optimal WCET-aware code selection for scratchpad memory
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
Hui Wu, Jingling Xue, Sridevan Parameswaran