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» On the Complexity of Register Coalescing
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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 11 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
WSCG
2003
185views more  WSCG 2003»
13 years 9 months ago
Complex 3D Feature Registration Using a Marching Template
The registration of 3D form features is essential to the supporting of reverse shape design processes. Extracting an editable shape feature from unordered data points is notorious...
Joris S. M. Vergeest, Sander Spanjaard, Chensheng ...
ISCA
1997
IEEE
104views Hardware» more  ISCA 1997»
13 years 11 months ago
Complexity-Effective Superscalar Processors
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
Subbarao Palacharla, Norman P. Jouppi, James E. Sm...
DAC
1997
ACM
13 years 11 months ago
A C-Based RTL Design Verification Methodology for Complex Microprocessor
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon ...
FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 11 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling