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CODES
2008
IEEE
14 years 2 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
SAC
2008
ACM
13 years 8 months ago
A self-balancing striping scheme for NAND-flash storage systems
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load eac...
Yu-Bin Chang, Li-Pin Chang
ISLPED
2004
ACM
75views Hardware» more  ISLPED 2004»
14 years 1 months ago
Preemption-aware dynamic voltage scaling in hard real-time systems
Dynamic voltage scaling (DVS) is a well-known low-power design technique for embedded real-time systems. Because of its effectiveness on energy reduction, several variable voltag...
Woonseok Kim, Jihong Kim, Sang Lyul Min
PDP
2011
IEEE
13 years 3 days ago
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
Jia Huang, Christian Buckl, Andreas Raabe, Alois K...
LISA
2007
13 years 10 months ago
Usher: An Extensible Framework for Managing Clusters of Virtual Machines
Usher is a virtual machine management system designed to impose few constraints upon the computing environment under its management. Usher enables administrators to choose how the...
Marvin McNett, Diwaker Gupta, Amin Vahdat, Geoffre...