115 search results - page 5 / 23 » On the Design of IEEE Compliant Floating Point Units |
CSSE
2008
IEEE
13 years 9 months ago
2008
IEEE
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
ARITH
2003
IEEE
14 years 1 months ago
2003
IEEE
This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic opera...
ARITH
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
CJ
2010
13 years 7 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...