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    » On the Design of IEEE Compliant Floating Point Units
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    ARITH
    1999
    IEEE
    92views Applied Computing» more  ARITH 1999»
    The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
    14 years 1 days ago
    The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
    Download  arith.stanford.edu
    Eric M. Schwarz, Ronald M. Smith, Christopher A. K...
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    ARITH
    2001
    IEEE
    106views Applied Computing» more  ARITH 2001»
    1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features
    13 years 11 months ago
    1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features
    Download  www.acsel-lab.com
    Ajay Naini, Atul Dhablania, Warren James, Debjit D...
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    CAL
    2007
    87views Software Engineering» more  CAL 2007»
    Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
    13 years 7 months ago
    Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
    Download  www.engr.uky.edu
    Abstract—Some processors designed for consumer applications, such as Graphics Processing Units (GPUs) and the CELL processor, promise outstanding floating-point performance for ...
    William R. Dieter, A. Kaveti, Henry G. Dietz
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    ARITH
    1999
    IEEE
    153views Applied Computing» more  ARITH 1999»
    Reduced Latency IEEE Floating-Point Standard Adder Architectures
    14 years 1 days ago
    Reduced Latency IEEE Floating-Point Standard Adder Architectures
    Download  arith.stanford.edu
    The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
    Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
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    ARITH
    2009
    IEEE
    174views Applied Computing» more  ARITH 2009»
    Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
    14 years 2 months ago
    Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
    Download  www.ac.usc.es
    The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand v...
    Jochen Preiss, Maarten Boersma, Silvia Melitta M&u...
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