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ASAP
2004
IEEE
171views Hardware» more  ASAP 2004»
13 years 11 months ago
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems
In this paper, we present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded ...
Vida Kianzad, Shuvra S. Bhattacharyya
IPPS
2000
IEEE
13 years 12 months ago
Dynamic Data Layouts for Cache-Conscious Factorization of DFT
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Vi...
IPPS
2007
IEEE
14 years 1 months ago
Optimizing Sorting with Machine Learning Algorithms
The growing complexity of modern processors has made the development of highly efficient code increasingly difficult. Manually developing highly efficient code is usually expen...
Xiaoming Li, María Jesús Garzar&aacu...
ICDCS
2010
IEEE
13 years 11 months ago
Stochastic Steepest-Descent Optimization of Multiple-Objective Mobile Sensor Coverage
—We propose a steepest descent method to compute optimal control parameters for balancing between multiple performance objectives in stateless stochastic scheduling, wherein the ...
Chris Y. T. Ma, David K. Y. Yau, Nung Kwan Yip, Na...
HPCA
2002
IEEE
14 years 8 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....