33 search results - page 6 / 7 » On the Extreme Parallelism Inside Next-Generation Network Pr... |
PDP
2010
IEEE
13 years 12 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
ICPP
2005
IEEE
14 years 1 months ago
2005
IEEE
Consider a heterogeneous cluster system, consisting of processors with varying processing capabilities and network links with varying bandwidths. Given a DAG application to be sch...
JOC
2010
13 years 2 months ago
2010
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
PADS
2009
ACM
14 years 2 months ago
2009
ACM
Abstract—In this paper we illustrate scalable parallel performance for the Time Warp synchronization protocol on the L and P variants of the IBM Blue Gene supercomputer. Scalable...
HPCA
2000
IEEE
14 years 12 hour ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...