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» On the Fault Testing for Reversible Circuits
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DATE
1997
IEEE
92views Hardware» more  DATE 1997»
13 years 11 months ago
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits
The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of al...
A. Dargelas, C. Gauthron, Yves Bertrand
VLSID
1996
IEEE
110views VLSI» more  VLSID 1996»
13 years 11 months ago
On test coverage of path delay faults
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 7 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
TC
1998
13 years 7 months ago
Optimal Zero-Aliasing Space Compaction of Test Responses
—Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The ...
Krishnendu Chakrabarty, Brian T. Murray, John P. H...
TASE
2009
IEEE
14 years 2 months ago
Fault-Based Test Case Generation for Component Connectors
The complex interactions appearing in service-oriented computing make coordination a key concern in serviceoriented systems. In this paper, we present a fault-based method to gene...
Bernhard K. Aichernig, Farhad Arbab, Lacramioara A...