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» On the Fault Testing for Reversible Circuits
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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 9 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
FPL
2011
Springer
195views Hardware» more  FPL 2011»
14 years 4 months ago
The Impact of Aging on an FPGA-Based Physical Unclonable Function
—On-chip Physical Unclonable Functions (PUFs) are emerging as a powerful security primitive that can potentially solve several security problems. A PUF needs to be robust against...
Abhranil Maiti, Logan McDougall, Patrick Schaumont
ICCAD
2008
IEEE
130views Hardware» more  ICCAD 2008»
16 years 1 months ago
Lightweight secure PUFs
— To ensure security and robustness of the next generation of Physically Unclonable Functions (PUFs), we have developed a new methodology for PUF design. Our approach employs int...
Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potk...
DFT
2005
IEEE
81views VLSI» more  DFT 2005»
15 years 10 months ago
Modeling QCA Defects at Molecular-level in Combinational Circuits
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...
Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi
ISLPED
2006
ACM
129views Hardware» more  ISLPED 2006»
15 years 10 months ago
Variation-driven device sizing for minimum energy sub-threshold circuits
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
Joyce Kwong, Anantha P. Chandrakasan