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IPPS
2000
IEEE
13 years 11 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
CCS
2003
ACM
13 years 12 months ago
Countering code-injection attacks with instruction-set randomization
We describe a new, general approach for safeguarding systems against any type of code-injection attack. We apply Kerckhoff’s principle, by creating process-specific randomized ...
Gaurav S. Kc, Angelos D. Keromytis, Vassilis Preve...
ISCA
2008
IEEE
205views Hardware» more  ISCA 2008»
14 years 1 months ago
VEAL: Virtualized Execution Accelerator for Loops
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
Nathan Clark, Amir Hormati, Scott A. Mahlke
CODES
1999
IEEE
13 years 11 months ago
An ASIP design methodology for embedded systems
A well-known challenge during processor design is to obtain the best possible results for a typical target application domain that is generally described as a set of benchmarks. O...
Kayhan Küçükçakar
LCTRTS
2004
Springer
14 years 1 days ago
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...