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EUROMICRO
2000
IEEE
14 years 2 days ago
A Simulink(c)-Based Approach to System Level Design and Architecture Selection
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
Luciano Lavagno, Begoña Pino, Leonardo Mari...
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
12 years 11 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
DATE
1998
IEEE
116views Hardware» more  DATE 1998»
13 years 12 months ago
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
Isidoro Urriza, José I. Artigas, José...
ICCSA
2005
Springer
14 years 1 months ago
Implementing Immersive Clustering with VR Juggler
Abstract. The last advances in commodity hardware have allowed users of immersive visualization to create high-performance systems using a set of interconnected computers. These sy...
Aron Bierbaum, Patrick Hartling, Pedro Morillo, Ca...
DSN
2005
IEEE
14 years 1 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh