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ASPDAC
2004
ACM
88views Hardware» more  ASPDAC 2004»
14 years 1 months ago
A high performance bus communication architecture through bus splitting
Abstract— A split shared-bus architecture with multiple simultaneous bus accesses is proposed. Compared to traditional bus architectures, the performance of proposed architecture...
Ruibing Lu, Cheng-Kok Koh
ICMCS
2006
IEEE
136views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Architecture Analysis for Low-Delay Video Coding
Low-delay video coding is a key technology for video conferencing as well as upcoming remote-monitoring and automotive video applications like rear-view cameras or night vision sy...
Ralf M. Schreier, A. Tushar Iqbal Rahman, Ganesh K...
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
13 years 11 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
13 years 12 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
ICIP
2009
IEEE
14 years 8 months ago
Memory-less Bit-plane Coder Architecture For Jpeg2000 With Concurrent Column-stripe Coding
In implementing an efficient block coder for JPEG2000, the memories required for storing the state variables dominate the hardware cost of a block coder. In this paper, we propose...