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ISCAS
2006
IEEE
95views Hardware» more  ISCAS 2006»
14 years 2 months ago
Vertex cache of programmable geometry processor for mobile multimedia application
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...
Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim
FCCM
2004
IEEE
96views VLSI» more  FCCM 2004»
14 years 8 days ago
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching
In this paper we advocate the use of pre-decoding for CAM-based pattern matching. We implement an FPGA based sub-system for NIDS (Snort) pattern matching using a combination of te...
Ioannis Sourdis, Dionisios N. Pnevmatikatos
VG
2003
13 years 10 months ago
Integrating Pre-Integration Into The Shear-Warp Algorithm
The shear-warp volume rendering algorithm is one of the fastest algorithms for volume rendering, but it achieves this rendering speed only by sacrificing interpolation between th...
Jürgen P. Schulze, Martin Kraus, Ulrich Lang,...
ICDE
2008
IEEE
218views Database» more  ICDE 2008»
14 years 10 months ago
AxPRE Summaries: Exploring the (Semi-)Structure of XML Web Collections
The nature of semistructured data in web collections is evolving. Increasingly, XML web documents (or documents exchanged via web services) are valid with regard to a schema, yet ...
Mariano P. Consens, Flavio Rizzolo, Alejandro A. V...
IPPS
2007
IEEE
14 years 2 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...