We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
We consider the problem of transmission scheduling of data over a wireless fading channel with hard deadline constraints. Our system consists of N users, each with a fixed amount...
Alessandro Tarello, Jun Sun 0007, Murtaza Zafer, E...
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Left unchecked, the fundamental drive to increase peak performance using tens of thousands of power hungry components will lead to intolerable operating costs and failure rates. H...