340 search results - page 28 / 68 » On the Interplay of Parallelization, Program Performance, an... |
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
WIOPT
2005
IEEE
14 years 2 months ago
2005
IEEE
We consider the problem of transmission scheduling of data over a wireless fading channel with hard deadline constraints. Our system consists of N users, each with a fixed amount...
ISPAN
2000
IEEE
14 years 26 days ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
SC
2005
ACM
14 years 2 months ago
2005
ACM
Left unchecked, the fundamental drive to increase peak performance using tens of thousands of power hungry components will lead to intolerable operating costs and failure rates. H...