340 search results - page 34 / 68 » On the Interplay of Parallelization, Program Performance, an... |
TVLSI
2010
13 years 3 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
With the increasing importance of energy consumption considerations and new requirements of emerging applications, in-network processing of information gains recognition as a viab...
IPCCC
2006
IEEE
14 years 2 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The expression of parallel codes through abstract, high-level specifications of global control and data flow can greatly simplify the task of creating large parallel prog...