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» On the Limits of Leakage Power Reduction in Caches
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ISCAS
2007
IEEE
110views Hardware» more  ISCAS 2007»
14 years 1 months ago
A Novel Active Decoupling Capacitor Design in 90nm CMOS
—On-chip decoupling capacitors (decaps) are generally used to reduce power supply noise. Passive decap designs are reaching their limits in 90nm CMOS technology due to higher ope...
Xiongfei Meng, Karim Arabi, Resve Saleh
HPCA
2009
IEEE
14 years 8 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
NOSSDAV
2009
Springer
14 years 2 months ago
Power efficient real-time disk scheduling
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...
Damien Le Moal, Donald Molaro, Jorge Campello
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
14 years 23 days ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
EUROPAR
2010
Springer
13 years 7 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...