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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
14 years 1 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
AUTOMATICA
2008
75views more  AUTOMATICA 2008»
13 years 10 months ago
Optimal complexity reduction of polyhedral piecewise affine systems
This paper focuses on the NP-hard problem of reducing the complexity of piecewise polyhedral systems (e.g. polyhedral piecewise affine (PWA) systems). The results are fourfold. Fi...
Tobias Geyer, Fabio Danilo Torrisi, Manfred Morari
JUCS
2000
91views more  JUCS 2000»
13 years 9 months ago
Syntax, Parsing and Production of Natural Language in a Framework of Information Compression by Multiple Alignment, Unification
This article introduces the idea that information compression by multiple alignment, unification and search (ICMAUS) provides a framework within which natural language syntax may ...
J. Gerard Wolff
DAC
2010
ACM
13 years 4 months ago
Node addition and removal in the presence of don't cares
This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing t...
Yung-Chih Chen, Chun-Yao Wang
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 7 months ago
Novel dual-Vth independent-gate FinFET circuits
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
Masoud Rostami, Kartik Mohanram