Sciweavers

7629 search results - page 285 / 1526
» On the Performance of a Survivability Architecture for Netwo...
Sort
View
SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
DSN
2009
IEEE
14 years 3 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
GECCO
2007
Springer
159views Optimization» more  GECCO 2007»
14 years 2 months ago
A systemic computation platform for the modelling and analysis of processes with natural characteristics
Computation in biology and in conventional computer architectures seem to share some features, yet many of their important characteristics are very different. To address this, [1]...
Erwan Le Martelot, Peter J. Bentley, R. Beau Lotto
IDMS
2001
Springer
133views Multimedia» more  IDMS 2001»
14 years 23 days ago
An Access Control Architecture for Metropolitan Area Wireless Networks
This paper introduces a novel access control architecture for publicly accessible, wireless networks. The architecture was designed to address the requirements obtained from a case...
Stefan Schmid, Joe Finney, Maomao Wu, Adrian Frida...
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
14 years 17 days ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood