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» On the Power of Positive Turing Reductions
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MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
14 years 2 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
ARC
2010
Springer
189views Hardware» more  ARC 2010»
14 years 7 days ago
3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable
Abstract. Few of the benefits of exploiting partially reconfigurable devices are power consumption reduction, cost reduction, and customized performance improvement. To obtain thes...
Thomas Marconi, Yi Lu 0004, Koen Bertels, Georgi G...
CP
2000
Springer
14 years 1 months ago
Expressiveness of Full First Order Constraints in the Algebra of Finite or Infinite Trees
We are interested in the expressiveness of constraints represented by general first order formulae, with equality as unique relation symbol and function symbols taken from an infi...
Alain Colmerauer, Thi-Bich-Hanh Dao
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
14 years 4 months ago
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
LMCS
2007
132views more  LMCS 2007»
13 years 9 months ago
The Complexity of Model Checking Higher-Order Fixpoint Logic
Higher-Order Fixpoint Logic (HFL) is a hybrid of the simply typed λ-calculus and the modal µ-calculus. This makes it a highly expressive temporal logic that is capable of express...
Roland Axelsson, Martin Lange, Rafal Somla