Adaptive techniques for overcoming performance degradation due to aging in digital circuits

— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guardbands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
• Keywords: ASPDAC 2009, Bias Temperature Instability, Hardware, Negative Bias Temperature Instability, Positive Bias Temperature